Parallel TX module configuration register0.
| TX_BYTELEN | Configures tx sending data byte length. |
| TX_GATING_EN | Write 1 to enable output tx clock gating. |
| TX_START | Write 1 to start tx global data output. |
| TX_HW_VALID_EN | Write 1 to enable tx hardware data valid signal. |
| TX_SMP_EDGE_SEL | Write 0 to enable sampling data on the rising edge of tx clock. Write 0 to enable sampling data on the falling edge of tx clock. |
| TX_BIT_UNPACK_ORDER | Write 0 to unpack bits from 1byte from MSB when data bus width is 4/2/1 bits. Write 0 to unpack bits from 1byte from LSB when data bus width is 4/2/1 bits. |
| TX_BUS_WID_SEL | Tx data bus width selection. 100: bus width is 1 bit 011: bus width is 2 bits 010: bus width is 4 bits 001: bus width is 8 bits 000: bus width is 16 bits |
| TX_FIFO_SRST | Write 1 to enable soft reset of async fifo in tx module. |